View CAT24C512HU5EGT3_7614189.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2012 october, 2012 ? rev. 4 1 publication order number: cat24c512/d cat24c512 512 kb i 2 c cmos serial eeprom description the cat24c512 is a 512 kb serial cmos eeprom, internally organized as 65,536 words of 8 bits each. it features a 128 ? byte page write buffer and supports the standard (100 khz), fast (400 khz) and fast ? plus (1 mhz) i 2 c protocol. write operations can be inhibited by taking the wp pin high (this protects the entire memory). external address pins make it possible to address up to eight cat24c512 devices on the same bus. on ? chip ecc (error correction code) makes the device suitable for high reliability applications. features ? supports standard, fast and fast ? plus i 2 c protocol ? 1.8 v to 5.5 v supply voltage range ? 128 ? byte page write buffer ? hardware write protection for entire memory ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial and extended temperature range ? 8 ? pin pdip, soic, tssop, msop and 8 ? pad udfn packages ? these devices are pb ? free, halogen free/bfr free and are rohs compliant figure 1. functional symbol sda scl wp cat24c512 v cc v ss a 2 , a 1 , a 0 http://onsemi.com pin configuration sda wp v cc v ss a 2 a 1 a 0 1 see detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. ordering information soic ? 8 w suffix case 751bd soic ? 8 x suffix case 751be scl pdip (l), soic (w, x), tssop (y), msop (z), udfn (hu5) pdip ? 8 l suffix case 646aa tssop ? 8 y suffix case 948al device address a 0 , a 1 , a 2 serial data sda serial clock scl write protect wp power supply v cc ground v ss function pin name pin function for the location of pin 1, please consult the corresponding package drawing. udfn ? 8 hu5 suffix case 517bu msop ? 8 z suffix case 846ad
cat24c512 http://onsemi.com 2 pdip ? 8 (l) soic ? 8 (w, x) tssop ? 8 (y) udfn ? 8 (hu5) marking diagrams 24512a = specific device code a = assembly location code y = production year (last digit) m = production month (1 ? 9, o, n, d) xxx = last three digits of assembly lot number = pb ? free microdot 24512a aymxxx c9l all ym 24512a axxx yywwg c12a aymxxx c12a = specific device code a = assembly location code y = production year (last digit) m = production month (1 ? 9, o, n, d) xxx = last three digits of assembly lot number = pb ? free microdot 24512a = specific device code a = assembly location code xxx = last three digits of assembly lot number yy = production year (last two digits) ww = production week (two digit) g = pb ? free designator c9l = specific device code a = assembly location code ll = last two digits of assembly lot number y = production year (last digit) m = production month (1 ? 9, o, n, d) = pb ? free microdot c9 = specific device code y = production year (last digit) m = production month (1 ? 9, o, n, d) a = assembly location code xx = last two digits of assembly lot number = pb ? free microdot msop ? 8 (z) c9ym axx
cat24c512 http://onsemi.com 3 table 1. absolute maximum ratings parameters ratings units storage temperature ?65 to +150 c voltage on any pin with respect to ground (note 1) ?0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (notes 3, 4) endurance 1,000,000 program/erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c. 4. the device uses ecc (error correction code) logic with 6 ecc bits to correct one bit error in 4 data bytes. therefore, when a single byte has to be written, 4 bytes (including the ecc bits) are re-programmed. it is recommended to write by multiple of 4 bytes in ord er to benefit from the maximum number of write cycles. table 3. d.c. operating characteristics v cc = 1.8 v to 5.5 v, t a = ? 40 c to +85 c and v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise speci ed. symbol parameter test conditions min max units i ccr read current read, f scl = 400 khz/1 mhz 1 ma i ccw write current v cc = 1.8 v 1.8 ma v cc = 5.5 v 2.5 i sb standby current all i/o pins at gnd or v cc t a = ? 40 c to +85 c 2 a t a = ? 40 c to +125 c 5 i l i/o pin leakage pin at gnd or v cc t a = ? 40 c to +85 c 1 a t a = ? 40 c to +125 c 2 v il1 input low voltage 2.5 v v cc 5.5 v ? 0.5 0.3 v cc v v il2 input low voltage 1.8 v v cc < 2.5 v ? 0.5 0.25 v cc v v ih1 input high voltage 2.5 v v cc 5.5 v 0.7 v cc v cc + 0.5 v v ih2 input high voltage 1.8 v v cc < 2.5 v 0.75 v cc v cc + 0.5 v v ol1 output low voltage v cc 2.5 v, i ol = 3.0 ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0 ma 0.2 v table 4. pin impedance characteristics v cc = 1.8 v to 5.5 v, t a = ? 40 c to +85 c and v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise speci ed. symbol parameter conditions max units c in (note 5) sda i/o pin capacitance v in = 0 v 8 pf c in (note 5) input capacitance (other pins) v in = 0 v 6 pf i wp , i a (note 6) wp input current, address input current (a 0 , a 1 , a 2 ) v in < v ih , v cc = 5.5 v 75 a v in < v ih , v cc = 3.3 v 50 v in < v ih , v cc = 1.8 v 25 v in > v ih 2 5. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 6. when not driven, the wp, a 0 , a 1 , a 2 pins are pulled down to gnd internally. for improved noise immunity, the internal pull ? down is relatively strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull ? down reverts to a weak current source.
cat24c512 http://onsemi.com 4 table 5. a.c. characteristics (note 7) v cc = 1.8 v to 5.5 v, t a = ? 40 c to +85 c and v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified. symbol parameter standard v cc = 1.8 v ? 5.5 v fast v cc = 1.8 v ? 5.5 v fast ? plus v cc = 2.5 v ? 5.5 v t a = ? 40 c to +85 c units min max min max min max f scl clock frequency 100 400 1,000 khz t hd:sta start condition hold time 4 0.6 0.25 s t low low period of scl clock 4.7 1.3 0.45 s t high high period of scl clock 4 0.6 0.40 s t su:sta start condition setup time 4.7 0.6 0.25 s t hd:dat data in hold time 0 0 0 s t su:dat data in setup time 250 100 50 ns t r (note 8) sda and scl rise time 1,000 300 100 ns t f (note 8) sda and scl fall time 300 300 100 ns t su:sto stop condition setup time 4 0.6 0.25 s t buf bus free time between stop and start 4.7 1.3 0.5 s t aa scl low to data out valid 3.5 0.9 0.40 s t dh data out hold time 50 50 50 ns t i (note 8) noise pulse filtered at scl and sda inputs 50 50 50 ns t su:wp wp setup time 0 0 0 s t hd:wp wp hold time 2.5 2.5 1 s t wr write cycle time 5 5 5 ms t pu (notes 8, 9) power-up to ready mode 1 1 0.1 1 ms 7. test conditions according to ?a.c. test conditions? table. 8. tested initially and after a design or process change that affects this parameter. 9. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i l = 3 ma (v cc 2.5 v); i l = 1 ma (v cc < 2.5 v); c l = 100 pf
cat24c512 http://onsemi.com 5 power-on reset (por) the cat24c512 incorporates power ? on reset (por) circuitry which pr otects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi ? directional por behavior protects the device against brown ? out failure, following a temporary loss of power. pin description scl: the serial clock input pin accepts the serial clock signal generated by the master. sda: the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address pins accept the device address. these pins have on ? chip pull ? down resistors. wp: the write protect input pin inhibits all write operations, when pulled high. this pin has an on ? chip pull ? down resistor. functional description the cat24c512 supports the inter ? integrated circuit (i 2 c) bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data flow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cat24c512 acts as a slave device. master and slave alternate as either transmitter or receiver. up to 8 devices may be connected to the bus as determined by the device address inputs a 0 , a 1 , and a 2 . i 2 c bus protocol the i 2 c bus consists of two ?wires?, scl and sda. the two wires are connected to the v cc supply via pull ? up resistors. master and slave devices connect to the 2 ? wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interpreted as a start or stop condition (figure 2). start the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake ? up? call to all receivers. absent a start, a slave will not respond to commands. stop the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. the stop starts the internal write cycle (when following a write command) or sends the slave into standby mode (when following a read command). device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8 ? bit serial slave address. the first 4 bits of the slave address are set to 1010, for normal read/write operations (figure 3). the next 3 bits, a 2 , a 1 and a 0 , select one of 8 possible slave devices. the last bit, r/w, specifies whether a read (1) or write (0) operation is to be performed. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9th clock cycle (figure 4). the slave will also acknowledge the byte address and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9th clock cycle. if the master acknowledges the data, then the slave continues transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by sending a stop to the slave. bus timing is illustrated in figure 5.
cat24c512 http://onsemi.com 6 start condition stop condition sda scl figure 2. start/stop timing figure 3. slave address bits 1010 device address a 2 a 1 a 0 r/w figure 4. acknowledge timing 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack setup ( t su:dat ) ack delay ( t aa ) figure 5. bus timing scl sda in sda out t buf t su:sto t su:dat t r t aa t dh t low t high t low t su:sta t hd:sta t hd:dat t f
cat24c512 http://onsemi.com 7 write operations byte write in byte write mode the master sends a start, followed by slave address, two byte address and data to be written (figure 6). the slave acknowledges all 4 bytes, and the master then follows up with a stop, which in turn starts the internal write operation (figure 7). during internal write, the slave will not acknowledge any read or write request from the master. page write the cat24c512 contains 65,536 bytes of data, arranged in 512 pages of 128 bytes each. a two byte address word, following the slave address, points to the first byte to be written. the most significant 9 bits (a 15 to a 7 ) identify the page and the last 7 bits identify the byte within the page. up to 128 bytes can be written in one write cycle (figure 8). the internal byte address counter is automatically incremented after each data byte is loaded. if the master transmits more than 128 data bytes, then earlier bytes will be overwritten by later bytes in a ?wrap ? around? fashion (within the selected page). the internal write cycle starts immediately following the stop. acknowledge polling acknowledge polling can be used to determine if the cat24c512 is busy writing or is ready to accept commands. polling is implemented by interrogating the device with a ?selective read? command (see read operations). the cat24c512 will not acknowledge the slave address, as long as internal write is in progress. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left floating or is grounded, it has no impact on the operation of the cat24c512. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the first data byte (figure 9). if the wp pin is high during the strobe interval, the cat 24c512 will not acknowledge the data byte and the write request will be rejected. delivery state the cat24c512 is shipped erased, i.e., all bytes are ffh.
cat24c512 http://onsemi.com 8 slave address s a c k a c k a c k s t o p p s t a r t a c k bus activity: master sda line byte address data figure 6. byte write timing a 15 ? a 8 a 7 ? a 0 figure 7. write cycle timing stop condition start condition address ack 8th bit byte n scl sda t wr slave address s a c k a c k a c k s t a r t a c k s t o p a c k a c k p a c k bus activity: master sda line byte address data data n data n+127 figure 8. page write timing a 15 ? a 8 a 7 ? a 0 figure 9. wp timing 189 1 8 address byte data byte scl sda wp t su:wp t hd:wp a 7 a 0 d 7 d 0
cat24c512 http://onsemi.com 9 read operations immediate address read in standby mode, the cat24c512 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. if that ?previous? byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. when, following a start, the cat24c512 is presented with a slave address containing a ?1? in the r/w bit position (figure 10), it will acknowledge (ack) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. the master can stop further transmission by issuing a noack, followed by a stop condition. selective read the read operation can also be started at an address different from the one stored in the internal address counter. the address counter can be initialized by performing a ?dummy? write operation (figure 11). here the start is followed by the slave address (with the r/w bit set to ?0?) and the desired two byte address. instead of following up with data, the master then issues a 2nd start, followed by the ?immediate address read? sequence, as described earlier. sequential read if the master acknowledges the 1st data byte transmitted by the cat24c512, then the device will continue transmitting as long as each data byte is acknowledged by the master (figure 12). if the end of memory is reached during sequential read, then the address counter will ?wrap ? around? to the beginning of memory, etc. sequential read works with either ?immediate address read? or ?selective read?, the only difference being the starting byte address. figure 10. immediate address read timing scl sda 8th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t figure 11. selective read timing slave address s a c k a c k a c k s t a r t slave s a c k s t a r t p s t o p byte address address n o a c k data bus activity: master sda line a 15 ? a 8 a 7 ? a 0 figure 12. sequential read timing s t o p p slave address a c k n o a c k data n bus activity: master sda line a c k data n+1 data n+2 a c k a c k data n+x
cat24c512 http://onsemi.com 10 package dimensions pdip ? 8, 300 mils case 646aa ? 01 issue a e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. symbol min nom max a a1 a2 b b2 c d e e1 l 0.38 2.92 0.36 6.10 1.14 0.20 9.02 2.54 bsc 3.30 5.33 4.95 0.56 7.11 1.78 0.36 10.16 eb 7.87 10.92 e 7.62 8.25 2.92 3.80 3.30 0.46 6.35 1.52 0.25 9.27 7.87
cat24c512 http://onsemi.com 11 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cat24c512 http://onsemi.com 12 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cat24c512 http://onsemi.com 13 package dimensions udfn8 3.0x2.0, 0.5p case 517bu ? 01 issue o dim min max millimeters a a1 0.00 0.05 b 0.20 0.30 d 2.00 bsc e 3.00 bsc e 0.50 bsc notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimensions b applies to plated terminal and is measured between 0.15 and 0.25 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. e2 pin 1 1 d e b a c 0.15 c 0.15 e note 3 a note 4 c a1 seating plane c 0.05 c 0.05 0.45 0.55 l 0.35 0.45 reference top view side view bottom view 1.06 3.30 0.50 dimensions: millimeters mounting footprint 1 b a c c 0.10 0.05 b 8x d pitch 0.63 0.32 outline pkg detail a (0.065) (0.127) detail a l recommended 8x 8x 4 8 5 8x d2 a m 0.10 b c m m a m 0.10 b c e2 0.85 0.95 d2 1.35 1.45 1.56
cat24c512 http://onsemi.com 14 package dimensions soic ? 8, 208 mils case 751be ? 01 issue o e1 eb side view top view e d pin#1 identification end view a1 a l c notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with eiaj edr-7320. symbol min nom max a a1 b c d e e1 e 0o 8o 0.05 0.36 0.19 5.13 7.75 5.13 1.27 bsc 2.03 0.25 0.48 0.25 5.33 8.26 5.38 l 0.51 0.76
cat24c512 http://onsemi.com 15 package dimensions msop 8, 3x3 case 846ad ? 01 issue o e1 e a2 a1 e b d c a top view side view end view l1 l2 l detail a detail a notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max a a1 a2 b c d e e1 e l 0o 6o l2 0.05 0.75 0.22 0.13 0.40 2.90 4.80 2.90 0.65 bsc 0.25 bsc 1.10 0.15 0.95 0.38 0.23 0.80 3.10 5.00 3.10 0.60 3.00 4.90 3.00 l1 0.95 ref 0.10 0.85
cat24c512 http://onsemi.com 16 example of ordering information (notes 10, 11) device order number specific device marking package type temperature range lead finish shipping (note 12) cat24c512le ? g 24512a pdip ? 8 ? 40 c to +125 c nipdau rail cat24c512li ? g 24512a pdip ? 8 ? 40 c to +85 c nipdau rail cat24c512we ? gt3 24512a soic ? 8, jedec ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cat24c512wi ? gt3 24512a soic ? 8, jedec ? 40 c to +85 c nipdau tape & reel, 3,000 units / reel cat24c512xe ? t2 24512a soic ? 8, eiaj ? 40 c to +125 c matte ? tin tape & reel, 2,000 units / reel cat24c512xi ? t2 24512a soic ? 8, eiaj ? 40 c to +85 c matte ? tin tape & reel, 2,000 units / reel cat24c512ye ? gt3 c12a tssop ? 8 ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cat24c512yi ? gt3 c12a tssop ? 8 ? 40 c to +85 c nipdau tape & reel, 3,000 units / reel CAT24C512HU5EGT3 c9l udfn8 ? 40 c to +125 c nipdau tape & reel, 3,000 units / reel cat24c512hu5igt3 c9l udfn8 ? 40 c to +85 c nipdau tape & reel, 3,000 units / reel cat24c512zi ? t3 c9 msop ? 8 ? 40 c to +85 c matte ? tin tape & reel, 3,000 units / reel 10. all packages are rohs-compliant (lead-free, halogen-free). 11. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor devic e nomenclature document, tnd310/d, available at www.onsemi.com 12. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 cat24c512/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of CAT24C512HU5EGT3

	To Download CAT24C512HU5EGT3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .